1. Field of the Invention
The present invention relates to a buffer circuit for driving a complementary metal-oxide semiconductor (C-MOS) inverter. More particularly, it relates to a buffer circuit for preventing simultaneous conduction of current through transistors in the C-MOS inverter during a transition of an input signal for the buffer inverter.
2. Description of the Prior Art
Generally, a conventional C-MOS inverter consists of a p-channel metal-oxide semiconductor (MOS) transistor (p-MOS) and an n-channel MOS transistor (n-MOS) connected in series between a power supply and a ground. In principle, no current flows from the power supply through the C-MOS inverter to ground in a steady state. This is because when one of the p-MOS or n-MOS transistors is conductive (turned on), the other is nonconductive (turned off). Therefore, there is no variation of the power supply voltage in the steady state.
During the transition period when the input of the C-MOS inverter is inverted, however, there is an instant when both transistors are conductive. At that instant, a large current flows through the C-MOS inverter. The large current causes a fluctuation in the power supply voltage, which is applied not only to the C-MOS inverter but also to the internal integrated circuit (IC) integrating the C-MOS inverter and other external circuits. The momentary variation in the power supply voltage is received by the internal IC or the external circuit as noise and often causes a circuit error operation. Therefore, it is necessary to prevent the momentary large current during the above-mentioned transition period. This is especially true when the C-MOS inverter is used as an output circuit of, for example, a memory circuit.
A C-MOS inverter is usually driven by two buffer circuits for respectively driving the p-MOS transistor and the n-MOS transistor in the C-MOS inverter. Conventionally, in order to prevent the large current during the above-mentioned transition period, the mutual conductances (gm) of the transistors, which constitute the buffer circuits are makes different from each other. This made the timing for driving the p-MOS transistor different from the timing for driving the n-MOS transistor. However, it is somewhat difficult to manufacture transistors in the buffer circuit having exactly the right mutual conductances for obtaining the desired time lag. Therefore, conventional buffer circuits cannot prevent the momentary large current during the transition period of C-MOS inverters.